Integrated thermistor and metallic element device and method

ABSTRACT

A circuit protection device includes a fuse element placed in parallel with a PTC thermistor layer. The element and PTC thermistor layer are provided on one or more insulating substrate, such as an FR-4 or polyimide substrate. First and second conductors connect the fuse element and PTC thermistor layer electrically in parallel, such that current (i) initially under normal flows mainly through the fuse element and PTC thermistor layer at a lower drop in voltage and (ii) after an opening of the fuse element flows under normal operation through the PTC thermistor layer at a higher drop in voltage.

BACKGROUND

The present disclosure relates generally to circuit protection and moreparticularly to overcurrent protection.

Fuses for printed circuit board (“PCB”) level applications have in manycases been resettable type fuses. The reason is that in many cases,PCB's are heavily populated, making the disposal of an entire PCB due toan opened non-resettable fuse impractical. Replacing an openednon-resettable fuse is also impractical. The PCB may be buried in amachine, automobile, computer, etc., in such a manner that it isvirtually impossible to reach. Even if reachable, the PCB may be in adevice, e.g., computer, cellular phone or other hand-held device that isused by an individual, making servicing difficult and/or costprohibitive.

One known resettable fuse that can be sized for PCB level applicationsis called a positive temperature coefficient (“PTC”) device. PTCthermistor materials rely on a physical characteristic germane to manyconductive materials, namely, that the resistivity of the conductivematerials increases with temperature. Crystalline polymers madeelectrically conductive via the dispersement of conductive fillerstherein, exhibit this PTC effect. The polymers generally includepolyolefins such as polyethylene, polypropylene and ethylene/propylenecopolymers. Certain doped ceramics such as barium titanate also exhibitPTC behavior.

The conductive fillers cause the resistivity of the PTC thermistormaterial to increase as the temperature of the material increases. Attemperatures below a certain value, the PTC thermistor material exhibitsa relatively low, constant resistivity. However, as the temperature ofthe PTC thermistor material increases beyond this point, the resistivityincreases sharply with only a slight increase in temperature.

If a load protected by a PTC thermistor material is short circuited, thecurrent flowing through the PTC thermistor material increases and thetemperature of the PTC thermistor material (due to the above-mentionedi²R heating) rises rapidly to a critical temperature. At the criticaltemperature, the PTC thermistor material dissipates a great deal ofpower causing the rate at which the material generates heat to begreater than the rate at which the material can lose heat to itssurroundings. The power dissipation only occurs for a short period oftime (e.g., a fraction of a second). However, the increased powerdissipation raises the temperature and resistance of the PTC thermistormaterial, limiting the current in the circuit to a relatively low value.The PTC thermistor material accordingly acts as a form of a fuse.

Upon interrupting the current in the circuit, or removing the conditionresponsible for the short circuit, the PTC thermistor material coolsbelow its critical temperature to its normal operating, low resistancestate. The result is a resettable overcurrent circuit protectionmaterial.

Even though the PTC thermistor materials operate at lower resistancesunder normal conditions, the normal operating resistances for PTCthermistor materials are higher than that of other types of fuses, suchas non-resettable metallic fuses. The higher operating resistanceresults in a higher voltage drop across the PTC thermistor material thanfor similarly rated non-resettable metallic fuses. Voltage drop andpower dissipation is becoming increasingly important to circuitdesigners, who are attempting to maximize the drive capability of aparticular circuit as well as battery life.

Accordingly, an improved PCB level circuit protection device is needed.

SUMMARY

The present disclosure relates in general to circuit protection and moreparticularly to overcurrent protection. While overcurrent causing eventsare relatively rare, especially in certain types of devices, they canstill occur and accordingly must be protected against. However, it hasbecome apparent that because the short circuit causing events arerelatively rare, a device and method adding a non-resettable, e.g.,metallic, type fuse element having a lower operating resistance inparallel with one or more resettable, e.g., positive temperaturecoefficient (“PTC”) thermistor, type fuse material provides a desirableoverall circuit protection combination.

The parallel combination results in an overall combined or equivalentresistance of the device, which is even lower than the operatingresistance of the metallic fuse element. In the unlikely event anovercurrent condition occurs, the metallic fuse element opens and theresistance of the PTC thermistor layer increases, limiting the currentand thereby protecting the circuit. When the overcurrent condition orshort circuit is removed, the PTC resistance decreases to its normaloperating value and the circuit functionality is restored, albeit at ahigher operating resistance than with the metallic fuse element intact.This approach offers the benefits associated with lower operatingresistance until an overcurrent condition occurs, which in most caseswill be the life of the circuitry since, as mentioned previously,overcurrent events are rare.

In one embodiment, therefore, a circuit protection device includes afuse element placed in parallel with a PTC thermistor layer. The elementand PTC thermistor layer are provided on one or more insulatingsubstrate, such as an FR-4 material or polyimide substrate. First andsecond conductors connect the fuse element and PTC thermistor layerelectrically in parallel, such that current (i) initially under normaloperation flows through both the fuse element and the PTC thermistorlayer causing a lower voltage drop, and (ii) after an opening of thefuse element flows under normal operation through the PTC thermistorlayer causing a higher voltage drop.

As shown below, the PTC thermistor layer and metallic fuse element inone embodiment can be configured to have approximately the sametime-current opening characteristic. The resulting combinationtime-current opening more closely tracks that of the PTC thermistormaterial, especially at higher currents. At lower currents, thecombination time-current opening characteristic is slower than eitherthe fuse element or PTC thermistor material. Alternatively, the PTCthermistor layer and metallic fuse element are chosen to have differentratings. For example, the PTC material can be chosen to have a lowerrating than the metallic fuse element.

In one embodiment the PTC thermistor layer is polymer based. In analternative embodiment, the PTC thermistor layer is ceramic. Theceramic-based integrated device can include a thin film type metallicfuse element or a wire fuse element as shown and described below. Theceramic-based device can be mounted via axially or radically disposedleads or be surface mounted.

The metallic fuse element is configured to provide desirable openingcharacteristics. For example, the metallic element, which can be copper,can be a surface-mounted element for which the length, thickness and/orheight of the element is set to provide a desired openingcharacteristic. Also, a dissimilar metal such as a Metcalf spot can beemployed to achieve a desired opening characteristic. The dissimilarmetal can be any one or more of nickel, indium, silver and tin.

The fuse element is alternatively a wire fuse element that is single ormulti-stranded. The wire can be of a single material or coated with adissimilar metal. The wire element is bonded, e.g., soldered, toelectrodes forming part of the first and second conductors.

The first and second conductors each include a pad or electrodeextending to each of the metallic fuse element and PTC thermistormaterial. An electrode can for example be formed by a photolithographicprocesses onto the insulating substrate. A PTC thermistor layer is thenapplied over the electrode and exposed substrate. An electrode can runfrom a termination of one of the conductors across most of the substratetowards a termination of the second conductor. The length of theelectrodes is sized to ensure good contact with the PTC thermistor layerand to allow the PTC thermistor material to function as desired.

In one embodiment, the fuse element is provided on one side of theinsulating substrate, while the PTC element is provided on the oppositeside of the substrate. In the case of a surface mounted device, theelement can be formed by photolithographic processes, e.g., from acopper layer, to have a thin, opening portion and wider pad portionsthat extend to terminal pads forming initial layers of end terminationsof the conductors. The copper pad is then plated with one or more layer,such as electrolytic copper and electrolytic tin. This plating operationforms vias or castellations to electrically connect the pads, electrodeand fuse element on each end of the device. The fuse element in anembodiment is provided with a protective cover, such as an epoxycoating. The fuse element side of the overall device in an embodiment isconfigured to be mounted towards the PCB, so that energy released uponan opening of the element is contained between the device and the PCB.

The device in one embodiment includes a plurality of insulatingsubstrates. For example, the fuse element can be located on the bottomside of a lower insulating substrate. A first conductor includes a firstelectrode applied (e.g., almost all the way across) to the topside ofthe bottom substrate. The PTC thermistor layer is then applied to theelectrode and to any exposed top of the bottom substrate. A secondinsulating substrate having a second electrode, e.g., formed byphotolithographic processes, on its bottom side is then applied to thetop of the PTC thermistor layer. The second electrode extends to thesecond conductor.

The topside of the second insulating substrate includes copper terminalpads. The upper terminal pads are plated the same as the lower terminalpads in one embodiment. The device can therefore be mounted in eitherdirection, for example, if it is determined in a particular instancethat mounting the device with the fuse element towards the PCB risksharming the integrity of the connection of the device to the PCB whenthe fuse element opens.

The topside of the upper insulating substrate can also be marked withsuitable indicia, such as rating indicia and manufacturer information.Again, in an embodiment, the fuse element is provided on the bottom sideof the bottommost substrate.

In a further alternative embodiment, one or more additional PTCthermistor layer and insulating substrates are added in the mannerdescribed above to produce a device having an overall desired operatingcharacteristic both when the metallic fuse element is intact and whenthe metallic fuse element has been opened. Adding PTC thermistor layersin general allows for the PTC side of the device to have a highercurrent rating and may need to be done to match the rating of themetallic fuse element.

In various embodiments, the device is provided in a 1206 (0.120 inch by0.06 inch) and 1812 (0.180 inch by 0.120 inch) packages.

It is accordingly an advantage of the present disclosure to provide animproved overcurrent protection device.

It is another advantage of the present disclosure to provide aresettable overcurrent device having reduced internal resistance andoperating voltage drop.

It is a further advantage of the present disclosure to provide aresettable overcurrent device having a metallic fuse element.

Additional features and advantages are described herein, and will beapparent from, the following Detailed Description and the figures.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a top plan view of one embodiment of an integrated resettableand non-resettable overcurrent protection device of the presentdisclosure.

FIG. 2A is a side-sectioned view of the integrated resettable andnon-resettable overcurrent protection device taken along line A-A ofFIG. 1 showing the terminations extending along the side of the device.

FIG. 2B is a side-sectioned view of the integrated resettable andnon-resettable overcurrent protection device taken along line B-B ofFIG. 1 showing the terminations not extending along the side of thedevice at the section.

FIG. 3 is a bottom plan view of the integrated resettable andnon-resettable overcurrent protection device of FIG. 1.

FIG. 4 is a schematic electrical diagram showing an example equivalentresistance for the parallel resettable and non-resettable overcurrentcomponents for the device of FIG. 1.

FIG. 5 is a time-current curve obtained from testing a sample of theintegrated resettable and non-resettable overcurrent protection deviceof FIG. 1.

FIG. 6 is a voltage drop versus current plot obtained from testingvarious samples of the integrated resettable e overcurrent protectiondevice of FIG. 1.

FIG. 7 is a side-sectioned view of an alternative integrated resettableand non-resettable overcurrent protection device of the presentdisclosure.

FIG. 8 is a side-sectioned view of one embodiment of an integratedresettable and non-resettable overcurrent protection device of thepresent disclosure, which uses a ceramic resettable overcurrentprotection material.

FIG. 9 is a side-sectioned view of another embodiment of an integratedresettable and non-resettable overcurrent protection device of thepresent disclosure, which uses a ceramic resettable overcurrentprotection material.

FIG. 10 is a side-sectioned view of a further embodiment of anintegrated resettable and non-resettable overcurrent protection deviceof the present disclosure, which uses a ceramic resettable overcurrentprotection material.

FIG. 11 is a side-sectioned view of yet another embodiment of anintegrated resettable and non-resettable overcurrent protection deviceof the present disclosure, which uses a ceramic resettable overcurrentprotection material.

FIG. 12 is a side view for any of the embodiments herein showing onesurface mounting configuration.

FIG. 13 is a schematic electrical view of a telecommunications circuitemploying a pair of integrated resettable overcurrent protection devicesof the present disclosure.

FIG. 14 is a schematic electrical view of a data bus circuit employingan integrated resettable overcurrent protection device of the presentdisclosure.

FIG. 15 is a schematic electrical view of a battery pack circuitemploying an integrated resettable overcurrent protection device of thepresent disclosure.

DETAILED DESCRIPTION

Referring now to the drawings and in particular to FIGS. 1, 2A, 2B and3, device 10 illustrates one embodiment of an integrated resettable andnon-resettable circuit protection device and associated method of thepresent disclosure. Device 10 includes an upper insulating substrate 12and a lower insulating substrate 14 (referred to herein collectively asinsulating substrates 12 or generally, individually as insulatingsubstrate 12). In an embodiment insulating substrates 12 are made of asame material, such as an FR-4 material or a polyimide. For example,substrate 12 can be supplied with a copper coating on both surfaces ofthe FR-4 material. The copper in one embodiment is then etched awayusing standard photolithographic processes to form various electrodepatterns. For example, the copper plating can be etched away to form anupper copper layer 20 a forming a base layer of terminations 36 a and 36b.

As seen in FIGS. 2A and 2B, second copper layer 16 is etched away frominsulating substrate 12 along the right side of device 10. In thismanner, electrode 16 does not directly electrically contact atermination formed at the right side of device 10. A similar thirdcopper layer or electrode 18 is etched onto the upper surface ofinsulating substrate 14. Here, electrode 18 makes contact with atermination formed on the right side of device 10 but does not directlyelectrically contact a similar termination formed on the left side ofdevice 10. A fourth copper layer 20 b is photo-etched away from thebottom side of insulating substrate 14 using standard photolithographicprocesses. As seen in the bottom of view FIG. 3 of device 10, copperlayer 20 b is etched to a specific shape to form the metallic fuseelement of device 10. Lower copper layer 20 b also extends to form abottom-side base layer of terminations 36 a and 36 b.

Insulating substrates 12 and 14 having etched copper layers 16, 18 and20 a and 20 b, respectively, are sandwiched about a positive temperaturecoefficient (“PTC”) layer 30. One suitable PTC thermistor material forPTC thermistor layer is provided in a Polyfuse® LF1206L device marketedby eventual assignee of the present disclosure. This material ispolymer-based. Ceramic configurations are discussed below.

PTC thermistor layer 30 in an embodiment is laminated initially betweentwo large insulating substrates. Electrodes 16, 18, 20 a and 20 b arepreformed on the large insulating substrates prior to their assembly,enabling many devices 10 to be formed from one assembled array. Device10 is then singulated from the assembled array of insulating substratesand attached PTC thermistor layer via known separation or singulationtechniques.

FIG. 3 illustrates that metallic fuse element 24 is formed on a bottomsurface of insulating substrate 14 in one embodiment. Copper layer 20 bis photo-etched to a specific shape to form the fuse element. Etchedcopper layer 20 b includes pad areas 22 a and 22 b, which extend toelement 24. Pad areas 22 a and 22 b also extend to larger terminationareas 26 a and 26 b of copper layer 20 b, which are eventually platedalong with upper copper layer 20 a to form terminations 36 a and 36 b.The base metal for fuse element 24 is therefore copper in oneembodiment.

While device 10 is generally described as having photo-etched copperelectrodes, it should be appreciated that electrodes 16, 18, 20 a and 20b could be made of alternative metals and applied via a differentprocess, such as an electroplating, sputtering, printing or laminating.Insulating substrates 12 can be made of a polyimide as opposed to anFR-4 material. Either way, electrodes 16, 18, 20 a and 20 b can be ofone or more metal, such as silver, copper, nickel, tin and alloysthereof applied to the surface of the polyimide in any of theabove-mentioned ways.

Element 24 has a height h, a length 1 and width w-sized to create adesirable opening characteristic for fuse element 24. Height h forexample can be thinner at element 24 than the height of pads 22 a and 22b and termination areas 26 a and 26 b. The thinned height h of element24 in an embodiment is formed via a skiving or additional etchingprocess. Element 24 is shown in FIG. 3 as having a generally straightlength 1. It should be appreciated however that element 24 canalternatively be jagged or curved, e.g., serpentine, to increase thedistance 1 as needed to create a desirable opening characteristic forelement 24.

Further, one or more dissimilar metal spot 28, sometimes referred to asa Metcalf spot, can be applied to element 24 at an area of the elementdesirable for the element to open, e.g., at the center of the element.Dissimilar metal spot 28 can be any one or more of nickel, indium,silver and tin. Dissimilar metal spot 28 has a lower melting temperaturethan that of the base metal of fuse element 24, e.g., copper. Lowmelting temperature spot 28 melts more quickly and diffuses into thebase metal of element 24. The base and dissimilar metals are chosen suchthat the diffusion of one into the other results in an intermetallicphase with a lower melting temperature and higher resistance than thebase metal, which forces the element to melt at lower level overcurrentlevels, and prevents over-heating of the device.

A protective coating 32 is applied to fuse element 24 and a portion offuse pads 22 a and 22 b as seen in FIGS. 2 and 3. Protective coating 32in an embodiment is an electrically insulating epoxy, which is printed,sprayed or otherwise applied to the bottom side of insulating substrate14 and copper layer 20 b forming fuse element 24, pad areas 22 a and 22b and termination areas 26 a and 26 b.

In an embodiment, device 10 is configured such that fuse element 24 ismounted towards the printed circuit board (“PCB”). Protective coating 32and the downwardly disposed mounting configuration tend to confine theenergy released from an opening of fuse element 24. It should beappreciated however that device 10 can operate alternatively with fuseelement 24 mounted towards the PCB or away from the PCB.

FIG. 1 illustrates a top surface of device 10. Here, indicia 34specifies rating and manufacturer information for device 10. Indicia 34in an embodiment is applied to, e.g., printed onto, a top surface ofupper insulating substrate 12.

Device 10 can be provided in various standard sizes, such as a 1206package, which is 0.120 inch by 0.06 inch (3.2 mm) by (1.6 mm).Alternatively, device 10 can be provided in an 1812 package, which isapproximately 0.179 inch by 0.127 inch (4.5 mm)×(3.24 mm). It should beappreciated however that device 10 can be made larger or smaller asdesired and to produce a device having a desired rating.

Terminations 36 a and 36 b are formed by standard plating techniques onthe upper and lower surfaces of device 10 in the illustrated embodiment.Terminations 36 a and 36 b can be multiple layers of metal, such aselectrolytic copper, electrolytic tin, silver, nickel or other metal oralloy as desired. Terminations 36 a and 36 b are sized and configured toenable device 10 to be mounted in a surface mount manner onto a PCB.

FIG. 2A illustrates a section A-A of FIG. 1 taken through the middle ofdevice 10. Accordingly, element 24 and dissimilar metal spot 28 are seenin FIG. 2A. A pair of apertures 46 and 48 is made in insulatingmaterials 12 and 14, for example, before device 10 is singulated fromthe device array. The plating of terminations 36 a and 36 b covers thesides of apertures 46 and 48. Accordingly, terminations extend along thesides of device 10 at the surfaces of apertures 46 and 48 as seen inFIG. 2A. When device 10 is singulated, terminations 36 a and 36 b do notextend along the straight sides of the device, e.g., do not extend alongthe straight sides of the device at section B-B of FIG. 1, as seen inFIG. 2B.

FIG. 4 illustrates an equivalent circuit for device 10 discussed above.The resistances shown in FIG. 4 are merely for the purposes of exampleand are in no way intended to limit the scope of the claims appendedhereto. The resistances do, however, represent realistic values for thepresent device. Thus PTC thermistor layer 30 (or the combination ofmultiple PTC thermistor layers 30) is shown for example having aresistance of 0.070 Ohms. Fuse element 24 has a lower resistance of0.031 Ohms. As seen in FIG. 4 and as should be appreciated from FIG. 2,PTC thermistor layer 30 and fuse element 24 are placed in electricalparallel with each other. According to the resistance equation forparallel devices, the equivalent resistance for device 10, E_(q) equalsthe PTC resistance R_(at) multiplied by the fuse resistance R_(f), whichforms a product that is divided by the sum of R_(at) plus R_(f). Thisequation yields an equivalent resistance in the example, R_(eq) of 0.022Ohms. The equivalent resistance is even less than the resistance of themetallic fuse element 24. Device 10 therefore has an initial lowresistance operation. Device 10 also has the ability to reset itselfthrough PTC thermistor layer 30.

According to the equivalent circuit of FIG. 4, the current willinitially pass through fuse element 24 and PTC thermistor layer 30 untilan overcurrent condition occurs, after which the current path throughelement 24 is opened and current is thereafter shunted in total undernormal operation through PTC thermistor layer 30. It is believed thatovercurrent events occur relatively infrequently, especially for certainapplications using device 10, meaning that in many cases device 10 willoperate without seeing an overcurrent condition throughout the entirelife of the PCB. That is, many devices 10 will operate under lowresistance and low voltage drop conditions throughout the entire life ofthe PCB. If however an overcurrent event does occur, device 10 maintainsits functionality and the PCB onto which it is mounted does not have tobe reworked or replaced. The original benefit of low resistance andvoltage drop is lost but overall functionality remains.

Referring now to FIG. 5, results from testing of a device 10 fortime-to-open versus current is illustrated. Three time-current curvesare illustrated, one for metallic a fuse element 24 rated for two Amps,one for PTC thermistor layer 30 rated for two Amps and one showing thetime-current curve for the two overcurrent components placed in parallel(combo). The combination line tends to follow that of PTC thermistorlayer 30 and has a longer response time than that of either fuse element24 or PTC layer 30.

The illustrated device 10 uses like rated fuse element 24 and PTCthermistor layer 30. Alternatively, device 10 can use a fuse element 24and PTC thermistor layer 30 having different ratings. For example, PTCthermistor layer 30 could have a lower rating, e.g., 1.5 Amps, than thetwo Amps of fuse element 24. The resulting device 10 would have aquicker response time, e.g., for a data bus application described inmore detail below. The telecommunications and battery applicationsdescribed below might require a slower acting overall device 10.

Referring now to FIG. 6, results for four parts made according to theteachings in connection with device 10 for voltage drop versus currenttesting are illustrated. The plot illustrates that the voltage drop forthe four parts was relatively repeatable, especially to about two Amps.Afterwards, the parts begin to show a slight variance. Also, theequivalent resistance of the device remains relatively constant over theillustrated current range. Further, the voltage drop across devices 10even at three Amps for all four parts tested was maintained under 100millivolts.

Referring now to FIG. 7 an alternative multi layer PTC device 50 isillustrated. Device 50 includes many of the same components discussedabove, such as fuse element 24 (and associated pads 22 a and 22 b andtermination areas 26 a and 26 b). Device 50 also includes a protectivecoating 32 covering fuse element 24 and a part of the fuse element padsas shown above. In one embodiment, device 50 is configured to mount suchthat fuse element 24 faces towards the PCB. Alternatively, device 50could be mounted in the opposite orientation. Device 50 also includesupper and insulating substrate 12 having, e.g., etched electrodes 20 aand 16 as described above. Marking text 34 is placed in one embodimenton a top surface of upper insulating substrate 12. Device 50 furtherincludes lower insulating substrate 14 having, e.g., etched upper andlower copper electrodes 18 and 20 b. Inner electrodes 16 and 18 as shownabove extend at least halfway across their associated substrates 12 and14 to create a desired opening characteristics for adjacent PTCthermistor layers 30 a and 30 b (referred to herein collectively as PTCthermistor layers 30 or generally, individually as PTC thermistor layer30).

Device 50 includes three PTC thermistor layers 30 a, 30 b and 30 c(collectively 30). Device 50 further includes two additional innerinsulating substrates 52 and 54 having, e.g., upper and lower electrodes38, 40, 42 and 44, respectively, which like electrodes 16 and 18 extendthe majority of the way across their respective insulated substrate 52,52, 54, and 54. Each of the electrodes 16, 18, 20 a, 30 b, 38, 40, 42and 44 can be etched or formed as otherwise described herein onto arespective FR-4 or polyimide insulating substrate 12. PTC thermistorlayers 30 are sandwiched between respective electrode bearing insulatingsubstrates via any of the methods described above. Device 50, likedevice 10, can be made as an array of devices 50, which are singulatedinto individual devices.

PTC thermistor layers 30 a to 30 c each operate the same as PTCthermistor layer 30 of device 10, namely, the layers are conductiveunder normal operating current loads. Upon an overload condition thatopens fuse element 24, PTC thermistor layers 30 heat up causing theirtemperatures and resistances to rise to a threshold point at which thetemperatures and resistances increase exponentially, resulting in ahighly resistive electrical path, akin to an open-circuit of fuseelement 24. The additional PTC thermistor layers for a given sizepackage increase the rating of the PTC component of device 50. Thuswhile three PTC thermistor layers 30 are shown with device 50, twolayers or four or more layers could be provided as needed to produce adevice 50 having a desirable fuse rating. The collective rating of PTCthermistor layers 30 can be the same or slightly different, e.g., lowerthan that of metallic element 24.

Referring now to FIG. 8, device 110 illustrates an alternativeintegrated metallic/PTC thermistor device. Here, PTC thermistor layer130 is ceramic-based as opposed to the polymeric material of thePolyfuse® LF1206L device. One suitable ceramic-based thermistor materialis disclosed in U.S. Pat. No. 6,218,928, entitled “PTC ThermistorMaterial”, assigned on its face to TDK Corporation (Tokyo, JP).

Device 110 includes an insulating substrate 112, which can for examplebe an ceramic material or glass. Upper and lower base electrodes 120 aand 120 b are formed respectively on upper and lower surfaces ofsubstrate 112 via thick film screen printing or sputtering. Electrodes120 a and 120 b can again be formed of one or more metal, such assilver, copper, nickel, tin and alloys thereof applied to the surface ofthe polyimide in any of the above-mentioned ways.

Base electrode 120 b is shaped to form the fuse element. Electrode 120 bfor example includes pad areas 122 a and 122 b extending inwardly toelement 124 and outwardly to larger termination areas 126 a and 126 b asshown above with electrode 20, pad areas 22, element 24 and terminationareas 26. Termination areas 126 a and 126 b are eventually plated alongwith upper copper layer 120 a to form terminations 136 a and 136 b.Metallic fuse element 124 of device 110 can have any of the shapes,dimensions and dissimilar metals discussed above for element 24 ofdevices 10 and 50.

A ceramic PTC (“CPTC”) thermistor layer 130 is located on a first sideof insulating base 112, e.g., via thick film screen printing or spincoating. As illustrated, CPTC thermistor layer 130 contacts portions ofelectrodes 120 a. An upper cover layer 132 a (e.g., fired glass) isapplied to CPTC thermistor layer 130 and exposed portions of electrodes120 a. Although not shown, marking indicia (discussed above) can beprovided on the top surface of CPTC thermistor layer 130 and be viewablethrough upper cover layer 132 a.

A lower cover layer 132 b (e.g., fired glass) is applied to lowerelectrode 120 b and exposed portions of substrate 112. Terminations 136a and 136 b are formed on the side edges of substrate 112, electrodes120 a and 120 b and cover layers 132 a and 132 b. Terminations 136 a and136 b also cover portions of the top and bottom surfaces, respectively,of, e.g., glass, cover layers 132 a and 132 b. Terminations 136 a and136 b can include multiple metallizations as discussed and shown above.Further, multiple CPTC thermistor layers 130 can be applied betweenmultiple insulating layers 112 in a manner similar to the polymericdevice of FIG. 7.

In operation, current flows from e.g., termination 136 a to termination136 b through upper and lower electrodes 120 a and 120 b and both CPTCthermistor layer 130 and the metallic fuse element in parallel until thefuse element opens. Upon the opening of the fuse element, CPTCthermistor layer 130 becomes highly resistive and limits the currenttraveling from termination 136 a to termination 136 b. When the powersurge has dissipated, CPTC thermistor layer 130 becomes conducting suchthat current can travel across device 110.

Referring now to FIG. 9, device 150 illustrates an alternativeintegrated metallic/CPTC thermistor device. Here again, CPTC thermistorlayer 130 is ceramic based as opposed to the polymeric material of thePolyfuse® LF1206L device. In device 150, CPTC thermistor layer 130doubles as the base substrate, taking advantage of the relatively rigidnature of the ceramic based material.

Upper and lower base electrodes 120 a and 120 b are formed respectivelyon upper and lower surfaces of CPTC thermistor layer 130 via thick filmscreen printing or sputtering. Electrodes 120 a and 120 b can be of oneor more metal, such as silver, copper, nickel, tin and alloys thereofapplied to the surface of CPTC thermistor layer 130 in any of theabove-mentioned ways.

In device 150, lower base electrode 120 b does not form the metallicfuse element but instead acts with CPTC thermistor layer 130, upper baseelectrode 120 a and terminations 136 a and 136 b to allow current toflow through CPTC thermistor layer 130 under normal operatingconditions.

A thin insulating layer 112, e.g., glass, is applied over lower baseelectrode 120 b and any exposed area of the bottom surface of CPTCthermistor layer 130. A third, fuse element electrode 152 is shaped ontosubstrate 112 to form the fuse element. Electrode 152 can for exampleinclude the same pad areas 122 a and 122 b extending inwardly to element124 and outwardly to larger termination areas 126 a and 126 b (shownabove in FIG. 8). The metallic fuse element of device 150 can have anyof the shapes, dimensions and dissimilar metals discussed above forelement 24 of devices 10 and 50 and element 124 of device 8.

An upper cover layer 132 a (e.g., glass) is applied to upper baseelectrode 120 a and exposed portions of CPTC thermistor layer 130.Although not shown, marking indicia (discussed above) can be provided onthe top surface of upper base electrode 120 a and be viewable throughupper cover layer 132 a.

A lower cover layer 132 b (e.g., glass) is applied to fuse elementelectrode 152 and exposed portions of substrate 112. Terminations 136 aand 136 b are formed on the side edges of CPTC thermistor layer 130,substrate 112, electrodes 120 a, 120 b and 152 and cover layers 132 aand 132 b. Terminations 136 a and 136 b also cover portions of the topand bottom surfaces, respectively, of, e.g., glass, cover layers 132 aand 132 b. Terminations 136 a and 136 b can include multiplemetallizations as discussed and shown above.

In device 150 operation, current flows from, e.g., termination 136 a totermination 136 b through upper electrodes 120 a, CPTC thermistor layer130, electrode 120 b and metallic fuse element layer 150 until the fuseelement opens. Upon the opening of the fuse element, CPTC thermistorlayer 130 becomes non-conducting and prevents current form travelingfrom termination 136 a to termination 136 b. When the power surge hasdissipated, CPTC thermistor layer 130 becomes conducting, such thatcurrent can travel again across device 150.

Referring now to FIG. 10, an alternative CPTC thermistor device 160 isillustrated. CPTC thermistor device 160 advantageously uses both upperand lower base electrodes 120 a and 120 b to contact both CPTCthermistor layer 130 and fuse element 162, which in the illustratedembodiment is a thick film, thin film or wire bonded fuse element. Fuseelement 162, shown as being generally vertically disposed, extends alongthe edge of the CPTC thermistor layer 130 from one base electrode 120 ato the other base electrode 120 b. The angle, shape and number of suchfuse elements can vary. Base electrodes 120 a and 120 b are also formedon both sides of CPTC thermistor layer 130 via any suitable techniqueand from any suitable one or more metal described above.

Device 160 in the illustrated embodiment also includes leads 164 and166, which can be radially or axially disposed for different mountingarrangements. In device 160 operation, current flows from e.g., upperelectrode 120 a (lead 164) to lower electrode 120 b (lead 166), throughCPTC thermistor layer 130 and fuse element 162 in parallel until thefuse element opens. Upon the opening of the fuse element, CPTCthermistor layer 130 becomes non-conducting and prevents current formtraveling from upper electrode 120 a (lead 164) to lower electrode 120 b(lead 166). When the power surge has dissipated, CPTC thermistor layer130 becomes conducting, such that current can travel again across device160.

Referring now to FIG. 11, an alternative CPTC thermistor device 170 isillustrated, which is the same as device 160 except that CPTC thermistorlayer 130 includes or defines a larger diameter hole or aperture 138configured to accept a diagonally disposed fuse element 172. Fuseelement 172 as shown is soldered or otherwise connected electrically tobase electrodes 120 a and 120 b located on opposite sides of aperture138. Element 172 is shown extending diagonally across the aperture. Thediagonal extension allows element 172 to be lengthened, which can bebeneficial for sizing purposes.

CPTC thermistor device 170 also disposes leads 164 and 166 on endplates174 and 176, respectively, which are in turn soldered to or otherwiseconnected to base electrodes 120 a and 120 b, respectively. Endplates174 and 176 cover aperture 138, protect fuse element 172 and connect thefuse element electrically to leads 164 and 166. Furthermore, theendplates allow the final part to be coated with a protective material,e.g., epoxy, maintaining a void in aperture 138, which improves thefusing performance of fuse element 172. Leads 164 and 166 are shownextending from endplates 174 and 176 in a radial fashion. Alternatively,leads 164 and 166 extend from endplates 174 and 176 in an axialdirection, e.g., as shown in FIG. 10.

The wire fuse element CPTC thermistor devices 160 and 170 operate thesame as the thin film CPTC thermistor devices 110 and 150, which operateat least substantially the same as the polymer based PTC thermistordevices discussed above. Current under normal operation flows throughboth CPTC thermistor layer 130 and fuse elements 124, 152, 162 or 172until an overcurrent event occurs. At such time, the fuse element opens,CPTC thermistor layer 130 becomes non-conducting, such that device 110,150, 160 or 170 does not allow the overcurrent to pass to electricalcomponents downstream of the device. When the overcurrent eventsubsides, CPTC thermistor layer 130 resets itself to a conducting state,allowing the protected circuit to function, albeit at a larger voltagedrop across device 110, 150, 160 or 170.

FIG. 12 shows a surface mount configuration for either of the devicesdescribed in FIG. 10 or 11. Here, the PTC or CPTC device includes endplates 182 and 184, each having a pad area 180 configured to be reflowor wave soldered to a printed circuit board. The illustrated embodimentshows a CPTC disk 130 (fuse element present but not seen), wherein endplates 182 and 184 and pad areas 180 connect the CPTC disk 130 and fuseelement electrically to a trace pattern on the printed circuit board.

Referring now to FIG. 13, circuit 60 illustrates one suitableapplication for device 10, 50, 110, 150, 160, 170 (referred to simply asdevice 10 hereafter for convenience) namely a telecom protectionapplication. Telecom protection circuit 60 includes a digitaltranscriber line (“DSL”) driver 62, which can be an interface cardlocated between downstream telecom equipment (not shown) and the datalines shown in FIG. 8. The telecom equipment can include equipment for acentral office switch, which switches calls from one point to another,e.g., switches digital voice or internet data.

DSL driver 62 conditions the signals and regenerates the signals to aswitch or other apparatus of the telecom equipment. DSL driver 62 is abi-directional transceiver that conditions signals sent in bothdirections over tip line 64 and ring line 66. Transformer 68 preventsdirect current (“DC”) residing on either side of the transformer frombeing propagated to the other side of the transformer. Transformer 68also cancels any noise or signal crosstalk from adjacent lines that arecoupled, and therefore common, to both the tip and ring lines.Transformer 68 accordingly couples differential signals.

Transient voltage suppressor 70 includes an overvoltage protectiondevice, such thyristor. Suppressor 70 can for example use a plurality ofdiodes positioned with a thyristor to reduce capacitance along any path,e.g., from tip line 64 to ring line 66, tip line 64 to ground 72, andground 72 to ring line 66. The diodes and thyristor are positioned suchthat each path has at least three capacitance reductions, providingheavily biased pathways that reduce the capacitance stepwise in seriesto a very low level that will not attenuate or discourage the datasignals.

Integrated fuse element/PTC device 10 are positioned in ring line 64 andtip line 66 to protect against an overcurrent condition due for exampleto a power-cross situation, in which a phone line or data line becomesinductively coupled to a power line, producing a continuous overvoltagecondition. Transient voltage suppressor 70 clamps the overvoltage at asafe level, dissipating a great deal of energy and triggeringovercurrent device 10.

If only a metallic element is used, the corresponding fuse in circuit 60has to be replaced. If only a PTC element is used, the resistance of thePTC element is substantially higher, limiting how far DSL driver 62 candrive the DSL signals down tip 64 or ring 66 lines. Because power-crossline conditions are rare, device 10 provides a resettable device thatoperates initially at a low resistance. If a power-cross condition doesoccur, the fuse element opens and the PTC device trips and eventuallyresets, such that circuit 60 still functions, at least at a limitedrange of data travel.

Referring now to FIG. 14, circuit 80 illustrates another application forintegrated fuse element/PTC device 10, namely, a data bus circuit. Theillustrated data bus circuit uses an IEEE 1394 controller 82, which isused with computers and other equipment, such as video cameras and cableboxes. Associated 1394 connector 84 is small, which is advantageous forthe above applications. Circuit 80 uses two twisted pair conductors TPAand TPB, which each transmit data bi-directionally between controller 82and connector 84.

Circuit 80 includes transient voltage suppressors 86 placed across thedata lines to ground 88. Voltage suppressors 86 suppress electrostaticdischarge (“ESD”) events occurring on data lines TPA and TPB. Circuit 80also includes a varistor 90, which suppresses ESD or other transientsoccurring on voltage line V_(bus) 92. V_(bus) is for example a 33 VDCsource that controller 82 uses to drive voltage down line 92 to powerwhatever is connected to connector 84, e.g., a printer or modem.

Integrated fuse element/PTC device 10 protects associated equipment fromany type of overcurrent condition occurring on power line 92. Hereagain, it is desirable that device 10 have as low a resistance aspossible, so that the voltage drop across the device is as low aspossible, and so that as much power can be delivered from controller 82to connector 84 and associated devices as possible. Device 10 isaccordingly well-suited for this application because it is unlikely thatline 92 will experience an overcurrent condition.

Device 10 can be used equally as effectively in universal serial bus(“USB”) data circuits and applications. Further, the devices can be usedin a powered Ethernet circuit. In a power over Ethernet circuit, two ofthe four twisted pairs in a Cat3/5 cable carry power and may also carrydata. Power delivery capability for such circuit is limited, makingdevice 10 well suited for such application.

Referring now to FIG. 15, circuit 100 illustrates a further applicationfor integrated fuse element/PTC device 10, namely, a battery protectioncircuit. Circuit 100 operates with a charger 94 for, e.g., a cellularphone 96. Control circuit 102 of battery pack circuit 100 senses avoltage supplied by charger 94. If, for example, the polarity of thevoltage is wrong, or the voltage level is wrong, controller 102 opensredundant field effect transistor (“FET”) switches 104 to stop anycurrent from flowing through circuit 100 to battery 108. Control circuit102 can also monitor temperature to look for thermal runaway. Here too,circuit 102 shuts down the current flow via switches 104 to battery 108.

PTC fuse device 10 provides a layer of redundant circuit protection. Forexample, if control circuit 102 does not operate properly or FET's 104become shorted, PTC fuse device 10 provides a backup layer ofovercurrent protection. Battery 106 of battery pack 100 varies in DCvoltage making the low resistance of device 10 important. For example,if an overcurrent device in a three VDC battery pack drops ¼ VDC, theover-current device consumes eight percent of the life of the battery.Battery 108 can have a drop-out voltage below which the cellular phonedoes not work, making the above life consumption percentage even higher.Thus a voltage drop in the millivolt range for device 10 in FIG. 6 iswell-suited for this application.

It should be understood that various changes and modifications to thepresently preferred embodiments described herein will be apparent tothose skilled in the art. Such changes and modifications can be madewithout departing from the spirit and scope of the present subjectmatter and without diminishing its intended advantages. It is thereforeintended that such changes and modifications be covered by the appendedclaims.

1. A circuit protection device comprising: an electrically insulating substrate; a fuse element located on the substrate; a positive temperature coefficient (“PTC”) thermistor layer connected to the substrate the fuse element having a lower resistance than the PTC thermistor layer, and first and second conductors connected electrically to the fuse element and the PTC thermistor layer in parallel, such that current (i) initially under normal operation flows through the fuse element and the PTC thermistor layer and (ii) after an opening of the fuse element flows under normal operation through the PTC thermistor layer.
 2. The circuit protection device of claim 1, wherein the fuse element and PTC thermistor layer have at least similar current ratings.
 3. The circuit protection device of claim 1, wherein the fuse element is of at least one a type selected from the group consisting of: (i) a wire, (ii) surface mounted, (iii) of a single metal, and (iv) of multiple metals.
 4. The circuit protection device of claim 1, wherein the first and second terminals include at least one attribute selected from the group consisting of: (i) first and second end terminations, (ii) extend onto first and second sides of the electrically insulating substrate, and (iii) are made of different metals.
 5. The circuit protection device of claim 1, wherein the fuse element and PTC thermistor layer are located on opposite sides of the insulating substrate.
 6. The circuit protection device of claim 1, wherein the substrate is made of a material selected from the group consisting of: FR-4, polyimide and glass.
 7. The circuit protection device of claim 1, the PTC thermistor layer being of a type selected from the group consisting of: polymeric and ceramic.
 8. The circuit protection device of claim 1, which includes a plurality of insulating substrates and a plurality of the PTC thermistor layers.
 9. The circuit protection device of claim 8, wherein the first and second conductors are each connected electrically to each of the PTC thermistor layers.
 10. A circuit protection device comprising: a first electrically insulting substrate; a fuse element located on a first side of the first insulating substrate; a first positive temperature coefficient (“PTC”) thermistor layer having a first side contacting a second side of the first substrate; a second electrically insulating substrate having a first side contacting a second side of the first PTC thermistor layer; a second PTC thermistor layer contacting a second side of the second insulating substrate; and first and second conductors connected electrically in parallel to the fuse element and the first and second PTC thermistor layers.
 11. The circuit protection device of claim 10, the fuse element having at least one attribute selected from the group consisting of: (i) being a surface mount element; (ii) having dissimilar metals; (iii) being of a wire bond type; and (iv) having a rating at least similar to that of a collective rating of the first and second PTC thermistor layers.
 12. The circuit protection device of claim 10, which includes a third electrically insulating substrate, the second PTC thermistor layer having a first side contacting the second side of the second insulating substrate and a second side contacting the third electrically insulating substrate.
 13. The circuit protection device of claim 10, wherein the first and second conductors each include at least one electrode contacting the fuse element and the first and second PTC thermistor layers.
 14. The circuit protection device of claim 10, wherein each of the first and second conductors includes an electrode extending at least halfway across one of the first and second PTC thermistor layers.
 15. The circuit protection device of claim 14, wherein the first and second conductors each include at least one end cap metallization contacting the electrodes.
 16. A circuit protection device comprising: a ceramic positive temperature coefficient (“CPTC”) thermistor layer; a fuse element carried by the CPTC thermistor layer, the fuse element having a lower resistance than the CPTC thermistor layer; and first and second conductors connected electrically to the fuse element and CPTC thermistor layer in parallel, such that current (i) initially under normal operation flows through the fuse element and the CPTC thermistor layer and (ii) after an opening of the fuse element flows under normal operation through the CPTC thermistor layer.
 17. The circuit protection device of claim 16, wherein the fuse element is a surface mount fuse element applied to the CPTC thermistor layer.
 18. The circuit protection device of claim 16, wherein the fuse element is a wire element affixed to electrodes applied to the CPTC thermistor layer.
 19. A circuit protection method comprising: protecting a first electrical pathway in a device with a non-resettable fusing apparatus having a relatively lower electrical resistance; and protecting a second electrical pathway in the device, and in parallel with the first electrical pathway, with a resettable fusing apparatus having a relatively higher electrical resistance, such that current (i) initially under normal operation flows through both the resettable and non-settable fusing apparatuses at a lower drop in voltage, and (ii) after an opening of the non-resettable fusing apparatus flows under normal operation through the resettable fusing apparatus at a higher drop in voltage.
 20. The circuit protection method of claim 19, wherein the resettable fusing apparatus includes a plurality of positive temperature coefficient layers.
 21. The circuit protection method of claim 19, including configuring the device for operation in a tip or ring line of a telecommunications circuit.
 22. The circuit protection method of claim 19, including configuring the device for operation in a voltage supply line between a data bus controller and a data bus connector.
 23. The circuit protection method of claim 19, including configuring the device for operation in a charging line of a battery pack. 